FIRST TUTORIAL- Analysis and Simulation of VHDL code:

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  • ******** IMPORTANT *********
  • * You must have set up the SYSTEM REQUIREMENTS, before attempting to go through the first tutorial. You should be in Synopsys/Code directory. Don't write your code in WORK directory.

    •  

    * Start with simple AND, OR, NOT, NAND, NOR, XOR gates then go for higher level design say FULL ADDERS.

    * EXAMPLE 1:

    Using any editor write the VHDL code for AND gate as given below and save it in file and.vhd

    ---------------------------------------------------------

    entity AND_2 is

    port

    (A, B : in BIT;

    Z : out BIT);

    end AND_2;

     

    architecture MODEL of AND_2 is

    begin

    Z <= A and B;

    end MODEL;

    ---------------------------------------------------------

     

    * For Analyzing (checking for errors) your code, at UNIX prompt give command :

    gvan and.vhd

     

    * For Simulation of your code, at UNIX prompt give command :

    vhdldbx

    *In vhdldbx - Select Simulator Arguments window select your analyzed design and press OK.

    * In the Synopsys VHDL Debugger window at the command prompt type:

    trace A B Z

    assign `1' A

    assign `1' B

    run 10

     

    * You can see results in Synopsys Waveform Viewer window.

     

    * For the elaboration of your design, at UNIX prompt give command :

    design_analyzer

     

    * In Synopsys Design Analyzer window, click on file/read the select and.vhd and press OK.

     

    EXAMPLE 2:

     

    In this example our design is composed of 3 AND gates.

     

    * Using any editor, write down the code of AND gate with 2 architectures as given below. Save it in file and2.vhd.

     

    ---------------------------------------------------------------

    entity ANDGATE_2 is

    port

    (X, Y : in BIT;

    Z : out BIT);

    end ANDGATE_2;

     

    architecture MODEL1 of ANDGATE_2 is

    begin

    Z <= X and Y;

    end MODEL1;

     

    architecture MODEL2 of ANDGATE_2 is

    begin

    process (X,Y)

    begin

    if X = '1' and Y = `1' then

    Z <= `1';

    else

    Z <= `0';

    end if;

    end process;

    end MODEL2;

    ----------------------------------------------------------------

     

    * Now using the above code of AND gate, write the code of above design (example 2), as given below. Save it in file ex2.vhd.

    -----------------------------------------------------------------------------------

    -- Interface

    entity EX_2 is

    port

    (A, B, C, D : in BIT;

    Z : out BIT);

    end EX_2;

     

    -- Body

    architecture STRUCTURE of EX_2 is

     

    -- Component Declaration

    component ANDGATE_2

    port

    (X, Y : in BIT;

    Z : out BIT);

    end component;

     

    for all : ANDGATE_2 use entity WORK.ANDGATE_2(MODEL1);

     

    -- Signal Declaration

    signal INT1, INT2 : BIT;

     

    begin

    -- Component Instanstiation

    A1 : ANDGATE_2 port map (A, B, INT1);

    A2 : ANDGATE_2 port map (C, D, INT2);

    A3 : ANDGATE_2 port map (INT1, INT2, Z);

     

    end STRUCTURE;

    ----------------------------------------------------------------------------------

     

    * Now for the simulation of EX_2 write down the test vector given below and save it in file test.

     

    -------------------------------------

    trace A B C D Z

     

    assign `0' /EX_2/A

    assign `0' /EX_2/B

    assign `0' /EX_2/C

    assign `0' /EX_2/D

    run 10

     

    assign `0' /EX_2/A

    assign `0' /EX_2/B

    assign `0' /EX_2/C

    assign `1' /EX_2/D

    run 10

     

    assign `0' /EX_2/A

    assign `0' /EX_2/B

    assign `1' /EX_2/C

    assign `0' /EX_2/D

    run 10

     

    assign `0' /EX_2/A

    assign `0' /EX_2/B

    assign `1' /EX_2/C

    assign `1' /EX_2/D

    run 10

     

    assign `0' /EX_2/A

    assign `1' /EX_2/B

    assign `0' /EX_2/C

    assign `0' /EX_2/D

    run 10

     

    assign `0' /EX_2/A

    assign `1' /EX_2/B

    assign `0' /EX_2/C

    assign `1' /EX_2/D

    run 10

     

    assign `0' /EX_2/A

    assign `1' /EX_2/B

    assign `1' /EX_2/C

    assign `0' /EX_2/D

    run 10

     

    assign `0' /EX_2/A

    assign `1' /EX_2/B

    assign `1' /EX_2/C

    assign `1' /EX_2/D

    run 10

     

    assign `1' /EX_2/A

    assign `0' /EX_2/B

    assign `0' /EX_2/C

    assign `0' /EX_2/D

    run 10

     

    assign `1' /EX_2/A

    assign `0' /EX_2/B

    assign `0' /EX_2/C

    assign `1' /EX_2/D

    run 10

     

    assign `1' /EX_2/A

    assign `0' /EX_2/B

    assign `1' /EX_2/C

    assign `0' /EX_2/D

    run 10

     

    assign `1' /EX_2/A

    assign `0' /EX_2/B

    assign `1' /EX_2/C

    assign `1' /EX_2/D

    run 10

     

    assign `1' /EX_2/A

    assign `1' /EX_2/B

    assign `0' /EX_2/C

    assign `0' /EX_2/D

    run 10

     

    assign `1' /EX_2/A

    assign `1' /EX_2/B

    assign `0' /EX_2/C

    assign `1' /EX_2/D

    run 10

     

    assign `1' /EX_2/A

    assign `1' /EX_2/B

    assign `1' /EX_2/C

    assign `0' /EX_2/D

    run 10

     

    assign `1' /EX_2/A

    assign `1' /EX_2/B

    assign `1' /EX_2/C

    assign `1' /EX_2/D

    run 10

    -----------------------------------

     

    * Now first analyze and2.vhd using command:

    gvan and2.vhd

     

    * Then alalyze ex2.vhd

    gvan ex2.vhd

     

    * For the simulation of ex2.vhd, at UNIX prompt write

    vhdldbx

     

    * Then in the Debugger window write

    include test

     

    * You can see the results in Result Viewer window.