Refereed Journal Papers (recent years)

· S. E. Esmaeili, A. J. Al-Khalili, "Integrated Power and Clock Distribution Network", IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, Oct. 2013, vol.21, No. 10, pp. 1941-1945.

· Ali Valaee, A.J. Al-Khalili,”High Performance Low Power Sensing
Scheme for Nanoscale SRAMs” in IET Computers & Digital Techniques Oct.2012.

· A. Nourivand, A. J. Al-Khalili, Y. Savaria, " Post Silicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-retention Failures ", IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, January 2012,Vol. 20, No.1 pp. 29-41.

· S. E. Esmaeili, A. J. Al-Khalili, G. E. R. Cowan, "Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks", IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, August 2012, vol.20, No. 8, pp. 1547-1551.

• A. Nourivand, A.J. Al-Khalili, Y. Savaria, “Analysis of Resistive Open Defects in Drowsy SRAM Cells” Journal of Electronic Testing: Volume 27, Issue 2 (2011), pp.203-214.
• S.E. Esameili, A.J. Al-Khalili, G.E.R. Cowan, "Dual edge triggered sense amplifier flip-flop for resonant clock distribution networks," IET Computers and Digital Techniques, volume 4, 2010, pp. 1-16.
• S.E. Esameili, A. Mohammadi Farhangi, G. Cowan, A.J. Al-Khalili, "Skew Compensation in Energy Recovery Clock Distribution Networks" IET Computers and Digital Techniques, volume 4, issue 1, January 2010, pp. 56-72.
• H. Saaied, D. Al-Khalili, A.J. Al-Khalili and M. Nekili "Simultaneous Adaptive Wire Adjustment and Local topology Modification for tuning a Bounded Skew Clock tree," IEEE Transactions on Computer Aided design of Integrated Circuits and Systems, Volume 24, No.10, pp. 1637-1643, Oct. 2005.
• A. Kabbani, D. Al-Khalili, A.J. Al-Khalili, "Delay Analysis of CMOS Gates Using Modified Logical Efforts Model," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.24, No. 6 , pp. 937-947, June. 2005.
• A. Kabbani, D. AlKhalili, A.J. Al-Khalili, " Technology portable analytical model for DSM CMOS inverter delay estimation" IEE Proc.-Circuits Devices Syst., Vol. 152, No. 5 October 2005, pp. 433-440.
• A. Kabbani, D. Al-Khalili, A.J. Al-Khalili, "Technology-Portable analytical Model for DSM CMOS Inverter Transition-Time      Estimation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.22, No. 9 , pp. 1177-1187, Sept. 2003.
• A. Kabbani, A.J. Al-Khalili, "Dynamic CMOS Noise Immunity" IEEE Transactions of Circuits and Systems Part I. Vol.50, No. 1, pp. 74-88, Jan.2003
• Yu Pai, A.J. Al-Khalili, W.E. Lynch, "Low-Power Constant-Coefficient Multiplier Generator, Journal of VLSI and Signal Processing Systems. Vol. 35, pp. 187-194, Sept. 2003
• Y. Pai, B. Lynch, A.J. Al-Khalili, "Low-power data-dependent 8x8 DCT/IDCT for video compression," IEE Proceedings, Vision, Image and Signal Processing. Vol. 150, No. 4, pp 245-255, Aug.2003.
• R.V. Pillai, D. Al-Khalili, A.J. Al-Khalili, S.Y. Shah, "Low Power Approach to Floating Point Adder Design for DSP Applications, "Journal of VLSI Signal Processing systems, Vol. 27, pp 195-213, 2001.
• R.V. Pillai, D. Al-Khalili, A.J. Al-Khalili, "Low Power Architecture for Floating Point MAC Fusion," Proceedings of IEE, Computers and Digital Techniques, Vol. 147, No. 4, pp128-134, July 2000.
• Kabbani, A.J. Al-Khalili, “Estimation of Ground Bounce Effects on CMOS Circuits,' IEEE Transactions of CPMT, vol., 22, No. 2, pp. 316-325 June 1999.
• H. Ahmed, A.J. Al-Khalili, L. Landsberger, M. Kahrizi, `A 2-D Micromachined accelerometer, 'IEEE Transactions on instrumentation and Measurements, Vol. 46, No. 1, pp18-26, Feb.97.
• S. Pagey, A.J. Al-Khalili, `Application of Byte error Detecting Codes to the Design of Self Checking Circuits,' International Journal of Microelectronics, Vol. 29 No.6. pp 323-333 June 98.
• S. Pagey, A.J. Al-Khalili, `Universal TSC module and its application to the design of TSC Circuits,' Int. Journal of Microelectronics, Vol. 28, No. 1 pp. 29-39, Jan. 1997.
• M. Esonu, A.J. Al-Khalili, S. Hariri. and D. Al-Khalili, `Design Techniques for Fault Tolerant Systolic Arrays," Journal of VLSI Signal Processing, Vol. 11, No. 1/2, pp. 151-168, Oct. 1995.
• M. Esonu, A.J. Al-Khalili, S. Hariri, `Area efficient Concurrent Error Detection for Systolic Arrays,' Journal of VLSI Signal Processing, Vol. 10, No.3, pp. 237-260, Aug. 1995.

Refereed Conference Proceedings,(Recent years)

· Book Chapters

· Houman Zarrabi, Zeliko Zilic, Yvon Savaria, Asim Al-Khalili,

· “ On the Efficient design & Synthesis of Differential Clock Networks,”
Source: VLSI, Book edited by: Zhongfeng Wang, ISBN: 978-953-307-049-0, Publisher: INTECH, Publishing date: February 2010

· Houman Zarrabi, A. J. Al-Khalili and Yvon Savaria

· "Design Intelligence for Interconnection Realization in Power-Managed SoCs" in *Computational Intelligence in Electronic Design*," Springer (2015).

· S. E. Esmaeili, A. M. Farhangi, A. J. Al-Khalili, G. E. R. Cowan, “Reduced wire length clock tree structure using the matched-delay skew compensation technique”, IEEE Canadian Conference on Electrical and Computer Engineering(CCECE), May 2012.

· Ali Valaee, and Asim J. Al-Khalili, “SRAM Read-Assist Scheme for High Performance Low Power Applications”, International SoC Design Conference (ISOCC 2011), Jeju, Korea, November, 2011.

· S. E. Esmaeili, A. J. Al-Khalili, G. E. R. Cowan, "Estimating required driver strength in the resonant clock generator", 2010 IEEE Asia Pacific Conference on Circuits and Systems, pp. 927-930, December 2010.

· Houman Zarrabi, A. J. Al-Khalili, and Yvon Savaria,” Repeater Insertion in Power-Managed VLSI systems” Proc. of GLSVLSI 2011, Lousane, Swizerland, May 10-12, 2011.

· Houman Zarrabi, A. J. Al-Khalili and Yvon Savaria, “A Fine-Grained Interconnect-Aware Dynamic Voltage Scaling Scheme for DSM VLSI,” ISCAS'10, Paris June 2010.

· Houman Zarrabi, A. J. Al-Khalili and Yvon Savaria, “Early Estimation of Energy Performance in Computing Platforms Utilizing Extensions to Amdahl’s Law,” International Conference on Electronics, Circuits, and Systems (ICECS), Dec 2009.

• H. Zarrabi, A.J. Al-Khalili, Y. Savaria, ”An Interconnect-Aware Delay Model for Dynamic Voltage Scaling in nm Technologies,” in Proc. of GLSVLSI 2009, Boston, Massachusetts, May 10-12, 2009.
• J. Athow, A.J. Al-Khalili, “Placement Algorithm for Multiplier-based FPGA Circuits," Proc. of ICM’08, Dec. 2008, Sharjah.
• S.E. Esmaeili, G. Cowan, A.J. Al-Khalili, “A Novel Approach for Skew Compensation in Energy Recovery Clock Distribution Networks, “in Proc. of ICM’08 Dec. 2008, Sharjah.
• M. Farhangi, A.J. Al-Khalili, “Via Minimization in Multi-layer Clock Distribution Network,” in Proc. SoC’08, Greece, Oct. 2008.
• Nourivand, A.J. Al-Khalili and Y. Savaria, "Aggressive Leakage Reduction of SRAMs Using Error Checking and Correcting Codes (ECC) Techniques,” in Proc. of 51st MWSCAS’08, Tennessee, 2008.
• J. Athow, A.J. Al-Khalili, “Implementation of Large Integer Multipliers in Xilinx FPGAs,” in Proc. of ICECS’08, Malta, 2008.
• S.E. Esmaeili, G. Cowan and A. J. Al-Khalili, "Dual-Edge Triggered Energy Recovery Flip Flop for Low energy Applications,” in Proc. of NEWCAS’08, Montreal, 2008.
• V. Konstantinos, T. Obuchowicz and A. J. Al-Khalili,” A CAD tool for the automatic generation of synthesizable parallel prefix adders in VHDL” in Proc. SPIE Microelectronics, MEMS, and Nanotechnology, Canberra, Australia. Dec. 2007.
• V. Konstantinos, Asim J. Al-Khalili, “Performance of Parallel Prefix Adders implemented with FPGA technology”, In proc. of NEWCAS’07, Montreal, Aug. 2007.
• H. Zarrabi, Z. Zilic, A.J. Al-Khalili, Y. Savaria, “A Simple Parallel Partitioning Algorithm for Zero Skew Differential Clock Distribution,” In proc. of NEWCAS ’07,Montreal, Aug. 2007.
• Cheung, B. Lynch, A.J. Al-Khalili , “Low power design of Motion Compensation Module for MPEG-4 Video Transcoder in DCT-domain,” In proc. of MWCAS ’07, Montreal, Aug. 2007.
• H. Zarrabi, H. Saaied, A.J. Al-Khalili, Y. Savaria, “Zero Skew Clock distribution Network,” in Proc. of ISCAS’06, Kos, Greece.
• Kabbani, D. Al-Khalili, A.J. Al-Khalili, “Logical Path Delay Distribution and Transistor Sizing,” Proc NEWCAS 05, Quebec City, 2005.
• Shaoqing Bi, W. Wang, A.J. Al-Khalili, “Multiplexer Based Binary Incrementor/Decrementor,” Proc NEWCAS 05, Quebec, 2005.
• Shaoqiang Bi, Warren J. Gross, Wei Wang, A. J. Al-Khalili, “An Area-reduced Scheme for Modulo 2^n-1 Addition/Subtraction, proc. 5^th workshop, System on Chip for real time applications, July 2005, Banff.
• Kabbani, D. Al-Khalili, A.J. Al-Khalili, “Delay Macro Modeling of CMOS Gates Using Modified Logical Effort Technique,” In Proc. ICSE2004, Kuala Lumpur Malaysia, pp. 56-60
• H. Saaied , Al-Khalili D, Al-Khalili A. J. “Clock Tree Routing Using Shortest Paths Polygon” in Proceedings of SOCC 2004, Santa Clara, CA, Sept. 12-15 2004, pp. 59-62.
• Kabbani, D. AlKhalili, A.J. Al-Khalili "Technology Portable Delay Model for DSM CMOS Inverters" In Proceedings of NEWCAS 04, Montreal, pp13-16.
• S. Deng, A.J. Al-Khalili. "A Technology Portable Analytical Model for DSM CMOS Inverter Short-Circuit Power Estimation" in Proceedings of NEWCAS 04, Montreal , pp101-104
• Bi, W. Wang and A.J. Al-Khalili, 'New Modulo Decomposed Residue-To-Binary Algorithm For General Modulo Sets,' in Proceedings of ICASSP'04, Montreal, May 2004. pp II-429-432.
• Bi, W. Wang and A.J. Al-Khalili, "Modulo Deflation In (2n +1, 2n, 2n -1) Converters" in Proceedings of at ISCAS’4, Vancouver, BC , May 2004 pp. V-141-144
• Kabbani A., Al-Khalili D, Al-Khalili A. J., “Technology Portable Analytical Model for DSM CMOS Inverter Transition Time Estimation.” IEEE International Mid West Symposium on Circuits and System, Cairo, Dec. 2003
• H. Saaied , Al-Khalili D, Al-Khalili A. J. “ Simultaneous Topology Optimization and Delay Cost Minimization of High Performance Nets with Obstacle constraints, In Proc. IEEE International Mid West Symposium on Circuits and System, Cairo, Dec. 2003
• H. Saaied , Al-Khalili D, Al-Khalili A. J. "Area Minimization of Clock Distribution Networks Using Local Topology Modification" Proc. of SOC 2003, Portland, Oregon, Sept 2003 pp. 227-230
• H. Saaied , Al-Khalili D, Al-Khalili A. J. "Adaptive Wire Adjustment and Local Topology Modification for Tuning Bounded Skew Clock Distribution Networks" NEWCAS'2003, June 17-19, pp. 193 -198, Montreal, Quebec
• Al-Khalili, A.Hu, "Design of a Targeted Squarer -Exploiting Addition Redundancy," ISCAS 2003, May 25-28, Bangkok, Thailand, PP. V325-V328, 2003.
• Aiping Hu, and A.J. Al-Khalili, "Comparison of Constant Coefficient Multipliers for CSD and Booth Recoding" proceedings of the 14th International Conference on Microelectronics, Beirut, Dec, 11-13, pp. 66-69.
• H. Saaied, D. Al-Khalili, A. J. Al-Khalili, M. Nekili, " Adaptive Wire Adjustment for Bounded Skew Clock Distribution Network Using Quadratic Tree," proceedings of the 14th International Conference on Microelectronics, Beirut, Dec. 11-13, pp. 19-23.
• H. Saaied, D. Al-Khalili, A. J. Al-Khalili, M. Nekili, " Quadratic Deferred-Merge Embedding Algorithm for Zero Skew Clock Distribution Network," in proceedings of TAU 2002, San Jose, Dec.6-9, 2002, pp. 119-125.
• H. Saaied, D. Al-Khalili, A. J. Al-Khalili, M. Nekili, "Adaptive Wire Adjustment for Bounded Skew Clock Distribution Network," in proceedings of ASP-DAC 2003, Kitakyushu, Japan, Jan. 21-24 2003, pp. 243-248
• Pai Cheng-Yu, A.J. Al-Khalili, W.E. Lynch, "Low Power Constant-Coefficient Multiplier Generator" ASIC/SOC 2001, Washington, Sept 2001.
• Najm-Uz Zaman, A.J. Al-Khalili, "32 bit Constant (k) Coefficient Multiplier,” In proceedings of TENCON 2001, Singapore, Aug. 2001.
• R.V.K. Pillai, S.Y.A. Shah, A.J. Al-Khalili, D. Al-Khalili, "Low Power Floating Point MAFs- A Comparative Study" In proceedings of the 6th ISSPA, Kuala Lumpur, Aug. 2001
• W. Islam, K. Khorasani, A.J. Al-Khalili, S. Tafazoli, "Development of algorithms for distributed and collaborative force feedback using Haptic Interfaces in virtual environments", in Proceedings of DASIA'2000, organized by Euro-Space, May 2000, Montreal.
• P. Sun, A.J. Al-Khalili, "A CAD Tool for First Hand CMOS Circuit Selection," Proceedings of 7th IEEE International Conference on Electronics, Circuits and Systems, pp. 165-168, Dec. 17-20, 2000.
• R.V. Pillai, D. Al-Khalili, A.J. Al-Khalili, "An IEEE Compliant Floating Point MAF," in Proc. of VLSI'99,Portugal, Dec. 99, pp. 165-168. System on a Chip, edited by L.M. Silveria. S. Devadas and R. Reis. Kluwer Academic Publishers. ISBN 0-7923-7731
• . A. Kabbani and A.J. Al-Khalili, `Dynamic CMOS Noise Immunity Estimation in Submicron Regime' Proc. of IEEE ISCAS 99, May 1999, pp.529-532.
• R.V. Pillai, D. Al-Khalili, A.J. Al-Khalili, 'Power Implications of Additions in Floating Point DSP- an Architectural Perspective. In Proc. of africon'99, Sept. 1999, 581-586.
• R.V. Pillai, D. Al-Khalili, A.J. Al-Khalili, 'An IEEE Compliant Floating Point MAF' In Proc. of VLSI'99, Portugal, Dec. 1999, pp.149-160.
• R.V. Pillai, D. Al-Khalili, A.J. Al-Khalili, ”Power Implications of Precision Limited Arithmetic in Floating Point FIR Filters' proc. of IEEE ISCAS 99, May 1999, pp. 165-168.
• A. Kabbani, A.J. Al-Khalili, `Estimation of Ground Bounce Effects on CMOS Circuits' Proc. of IEEE ISCAS 99, May 1999 pp. 533-536.
• R.V. Pilai, D. Al-Khalili, A.J. Al-Khalili, 'Arithmetically sub-optimal Floating point Digital Filters- an architectural Power Perspective. Proc. of CCECC'99, Edmonton Canada. pp 589-592.
• J. Augustine, B. Lynch, Y. Wang, and A.J. Al-Khalili, “Lossy Compression of Images Using Logic Minimization,' Proc. of 12th International Conference on VLSI Design, VLSI'99, India, Jan. 99 pp.538-543.
• .A. Kabbani, and A.J. Al-Khalili, `Dynamic Noise Immunity,' Proc. of International Conference on Microelectronics. ICM'98 Dec. 1998 pp. 41-44.
• R.V. Pillai, D. Al-Khalili, A.J. Al-Khalili, `On the Power Implications of Floating Point Addition in IIR Filters,' Proc. of International Conference on Microelectronics. ICM'98 Dec. 1998 pp200- 203.
• R. Pillai, D. Al-Khalili, A.J. Al-Khalili, `On the Distribution of Exponent Differences During Floating Point addition,' in Proc. Canadian Conference on Electrical and Computer Engineering, Waterloo, Ontario, May 24-27, 1998.pp.105-108.
• R. Pillai, A.J. Al-Khalili, D. Al-Khalili, `A Low Power Floating Point Accumulator,' VLSI'98 Chennai India, Jan. 1998, pp. 330-333.
• R. Pillai, D. Al-Khalili, A.J. Al-Khalili, `Energy Delay Measures of Barrel Architectures for Pre- Alignment of Floating Point Operands for Addition,' Proc. 1997 Int. Symp. Low Power Electronics and Design, Monterey, CA, pp. 235-238.Aug.18-20, 1997.
• R. Pillai, D. Al-Khalili, A.J. Al-Khalili, `Evaluation of 1's Complement Arithmetic for the Implementation of Low Power CMOS Floating Adders,' Proc. of CCECE'97, St. John Newfoundland, May 97, pp. 153-156.
• S. Shehata, B. Haroun, A.J. Al-Khalili, `Performance & Clock Determination for Synthesis of DSP Cores Targeting FPGA's,' IN proc. ASICs 96, Sept. 23-27, 1996, Rochester, pp. 151-154,. H. Ahmed, A.J. Al-Khalili, L. Landsberger, M Kahrizi, `A 2D Micromachined Accelerometer,' in proc. 3rd IEEE International Conference on Electronics, Circuits and Systems, Rodeos Oct. 12- 16, 1996, pp 908-911.
• S. Shehata, B. Haroun, A.J. Al-Khalili, `Rapid Prototyping of High Performance DSP Structures Targeting FPGA's,' in proc. ICSPAT 96, Oct. 1996, Boston, pp. 1575-1579.
• S. Shehata, B. Haroun, A.J. Al-Khalili, `A Methodology for High Level Synthesis of High Performance DSP Structured Architecture Targeting FPGA's,' in proc. ASICON 1996, Oct. 96, Shanghai, pp. 89-92.

Book Chapters

Houman Zarrabi, Zeliko Zilic, Yvon Savaria, Asim Al-Khalili,

“ On the Efficient design & Synthesis of Differential Clock Networks,”
Source: VLSI, Book edited by: Zhongfeng Wang, ISBN: 978-953-307-049-0,

Publisher: INTECH, Publishing date: February 2010

Houman Zarrabi, A. J. Al-Khalili and Yvon Savaria

"Design Intelligence for Interconnection Realization in Power-Managed SoCs" in *Computational Intelligence in Electronic Design*," Springer (2015).