To the question "What is the difference between VHDL and Verilog?" Ted Obuchowicz 
(our VLSI Engineer/CAD Specialist) humorously replied:

The differences between VHDL and Verilog are akin to the differences between a
Fender Telecaster electric guitar and a Gibson Les Paul electric; both produce the
same end result. A choice of one over the other is usually dictated by personal
preferences, much as anything else in life. Are the Rolling Stones a better band
than the Beatles (my answer is an unequivocal yes), is a Ferrari F50 a better car
than a Lamborghini Diablo (I'll never know, Concordia does not pay me enough to
ever find out), is summer better than winter? (yes...)

Both Verilog and VHDL are IEEE standards.  Verilog started life as a simulation
input language for a proprietory simulator (ie. Gateway Design Automation).  
Cadence eventually purchased Gateway Design and make the Verilog language open.  
The Open Verilog Initiative promulgated the standardization effort which eventually
led the the IEEE standard of Verilog.  VHDL was a US Department of Defense funded
project originally meant as a documentation language.  It eventually found use as a
simulation language.  In the 1980's , people realized that it could be used as an
input to a logic synthesis tool.. the rest is history as the saying goes...

Some people claim that Verilog is "easier" to learn, others claim VHDL is more
powerful. Most, if not all synthesis tools accept RTL code in either language.  
Layout tools (in particular Cadence's Silicon Ensemble) accept netlists in Verilog
format.  A good digital design engineer would do well to learn both languages (I am
fluent in VHDL, and adequate with Verilog - I prefer VHDL over Verilog and Fenders
over Gibsons).

Hardware Description Languages are evolving, the latest buzzword is something
called SystemC ( a hardware description language based on the C++ programming
language together a class library used to model hardware ). The impetus for these C
-type of hdl is co-simulation of your hardware and the software intended to run on
the hardware.  The task of writing high-level testbenches is greatly simplified if
a high-level programming language is used.