MOS Current Mode Logic (MCML) circuits have found widespread use in recent years due to their capability to operate with lower signal voltages at ultra high frequency applications and at lower supply voltages than conventional CMOS. Although they dissipate more static power dissipation and have a larger layout area, the aforementioned properties make them the best choice for high speed applications [1].

With advances in recent years and scaling down to sub-100nm, CMOS technology suffers from increasingly severe process-induced variability [2]. Because of increased relative variation in transistor parameters, each device shows more variation in performance as device size scales down [3].Although a smaller CMOS process allows for even wider use of CML circuits (despite their larger area), process variation may degrade system performance. Therefore, it is worth looking at such variation in more detail.

The conventional method that would be used to overcome such deviation is the replica biasing scheme [4]. Although this method is satisfactory for many applications, variations in DC-gain will still be present. In this project, an oscillator-based scheme is examined which can tightly regulate the DC gain of CML circuits. Because DC gain and delay for CML circuits are highly correlated, reductions in DC gain variation also lead to reductions delay variation. The proposed technique reduced DC gain variation to 1/7th that achieved by replica bias.

[1]      P. Heydari and R. Mohavavelu, “Design of ultrahigh speed CMOS CML buffers and latches,” in Proc. Int. Symp. Circuits Syst.,May 2003, vol. 4, pp. 169–172.

[2]     C. Cho et al.,“Decomposition and analysis of process variability using constrained principal component analysis,” IEEE Trans. Semicond. Manuf., vol. 21, no. 1, pp. 55–62, Feb. 2008.

[3]     D. Kim, C. Cho, J. Kim, J. Plouchart, R. Trzcinski, and D. Ahlgren, “CMOS mixed-signal circuit process variation sensitivity characterization for yield improvement,” in Proc. IEEE Custom Intergr. Circuits Conf., Nov. 2006, pp. 365–368.

[4]     I. Young, J. Greason, J. Smith, and K. Wong, “A PLL clock generator with 5 to 110 MHz lock range for microprocessors,” in ISSCC 1992 Dig. Tech. Papers, pp. 50–51.