Analog implementations of TS-LDPC decoders
 Prospective Students




Investigator:  Alireza Rabbani, PhD student. Co-supervised by Drs. Yousef Shayan and Glenn Cowan

A general communication system consists of three basic sections: transmitter, communication channel and receiver. The transmitter’s task is to convert information bits to signals that can be transmitted over the channel. The channel is the physical medium used to send signals from the transmitter to the receiver. The receiver is the end of a communication system, which detects the information bits with the lowest possible probability of error. To minimize the number of errors at the output of the receiver and consequently having more reliable communication over noisy channels, error control codes are introduced. Increasing demand for using wireless communication systems and expecting good quality of service have shifted the researchers’ focus towards designing more efficient codes with less complexity. In single antenna wireless communication systems, the Shannon capacity limit can be achieved through advanced codes, such as Turbo codes and Low Density Parity Check (LDPC) codes.

Low-Density Parity Check codes are a class of linear block codes that have sparse parity check matrices (H). LDPC codes have been adopted in the latest communication and storage systems due to their linear decoding complexity and superior error performance. LDPC code applications are including but not limited to, Digital Video Broadcasting (DVB-S2), 10Gigabit Ethernet (10GBASE-T), broadband wireless access (WiMax), wireless local area network (WiFi), deep-space communications and magnetic storage in hard disk derives.

LDPC codes are constructed randomly or structurally. Structured codes are more interesting due to their regularity. In this project we consider a class of structured regular LDPC codes, called Turbo-Structured LDPC (TS-LDPC) codes. TS-LDPC codes can be designed with any arbitrary desired column weight, row weight and girth (the shortest cycle in their graphical representation). Large girth guarantees large minimum Hamming distance (dmin) between the codewords, resulting in TS-LDPC codes’ lower error floor at high Signal to Noise Ratio (SNR). Their Parity check matrix (H) can be constructed from a much smaller shift matrix S which saves a great amount of memory. It has been shown that TS-LDPC codes outperform the randomly generated LDPC codes at higher SNR and have much lower noise floor. Therefore, TS-LDPC codes are a good candidate to be adopted in communication applications, which needs low bit error rate at higher SNR.

Recently, implementation of analog decoders has been targeted as a re-search direction by many VLSI research groups. Analog decoders are preferred in many communication systems due to their higher speed, lower power dissipation and smaller chip area compared to their digital counterpart. Analog decoders are suitable for the decoding algorithms using iterative schemes such as the Sum-Product algorithm. The SP algorithm is the best performing and also the most complex algorithm for decoding LDPC codes. Another algorithm with almost the same performance but less complexity is known as the Min-Sum (MS) algorithm. MS algorithms are preferable since the complexity of computations performed in nodes is much lower than in the case of the SP algorithm.

Previously, TS-LDPC codes have been investigated using the SP algorithm. However, to optimally use them in an analog decoding context their superior error floor should be evaluated using the MS algorithm. We have adapted MS algorithm in the decoding of TS-LDPC codes and evaluated the decoding performance to verify that the property of low error floor is maintained when the MS algorithms are used. It is shown that MS algorithm can be a good candidate for the implementation of TS-LDPC analog VLSI decoder.

Since the goal of this project is to design and fabricated an MS algorithm based TS-LDPC analog decoder, therefore the suitability of the decoder is tested. Some analog impairments such as mismatch, leakage and noise are considered in the decoding procedure of TS-LDPC codes. It is shown that the degradation of the error performance of TS-LDPC codes due to analog impairments is negligible. Therefore, it can be concluded that the analog decoder of TS-LDPC code using MS algorithm is fairly robust against analog imperfections. We are currently working on the design of the analog decoder.