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Low-power design is becoming a crucial design objective due to the
growing demand on portable applications and the increasing difficulties
in cooling and heat removal. Microprocessor power consumption is
increasing by approximately 20% per year. Nearly half of that power is
being dissipated in the clock distribution network. Resonant clocking
is an emerging promising technique to reduce the power of the clock
network. The inductor used in resonant clocking enables the conversion
of the electric energy stored on the clock capacitance to magnetic
energy in the inductor and vice versa.
My project goals are to propose novel low-power schemes and to modify traditional low-power techniques to reduce the power consumption of the clock distribution network with emphasis on the clock sink, i.e., the flip-flops operating under resonant (sinusoidal) clocking.
A new type of slack in the skew has been proposed [1], [2]. This new slack can be compensated for to reduce routing complexity in the clock network and as a byproduct achieve reduction in wire elongation, total wire length, and power. Simulation results illustrate that the proposed approach is feasible and effective where a reduction of 53% in the number of wire elongations has been achieved. In addition, a dual-edge clocking scheme introduced in the literature to enable the operation of the flip-flop at the rising- and falling edges of the clock has been modified. The interval by which the charging elements in the flip-flop are being switched-on was reduced causing a reduction in power consumption [3], [4]. Simulating the flip-flop in STMicroelectronics 90nm technology show correct functionality of the flip-flop with a resonant clock signal of 500MHz and a throughput of 1GHz under process, voltage, and temperature (PVT) variation. Modeling the resonant system with the proposed flip-flop illustrates that dual-edge triggering can achieve up to 58% reduction in power consumption. Furthermore, the application of low-swing clocking to resonant clock distribution network is being investigated. The proposed low-swing resonant clocking scheme operates with one voltage supply and does not require an additional supply voltage. The Differential Conditional Capturing Energy Recovery flip-flop introduced in the literature was modified to operate with a low-swing sinusoidal clock. The layout of a multiply and accumulate unit using the proposed flip-flop with the low-swing clock has been submitted for fabrication using TSMC 90nm technology. The power advantages of low-swing clocking will be investigated on-chip.
Though the project concentration is aimed at the flip-flop side, estimating the power savings achievable through dual-edge and low-swing clocking required estimating the power of the clock driver. In doing so, an analytical approach was introduced to estimate the required driver strength in the clock generator. Using the proposed approach early at the design stage eliminates the need for programmable switches in the driving circuit, thus reduces area and power overhead.
References
1- S. E. Esmaeili, A. M. Farhangi, A. J. Al-Khalili, G. E. R. Cowan, (January 2010) ‘Skew compensation in energy recovery clock distribution networks’, IET Computers and Digital Techniques, vol. 4, issue 1: 56 – 72
2- S. E. Esmaeili, A. J. Al-Khalili, G. E. R. Cowan, (December 2008) ‘A novel Approach for skew compensation in energy recovery clock distribution networks’, IEEE 20th International Conference on Microelectronics, IEEE-ICM: 365 – 368
3- S. E. Esmaeili, A. J. Al-Khalili, G. E. R. Cowan, (Accepted – May 2010) ‘Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks’, IET Computers and Digital Techniques, 16 pages
4- S. E. Esmaeili, A. J. Al-Khalili, G. E. R. Cowan, (June 2010) ‘Dual-edge triggered pulsed energy recovery flip-flops’, 8th IEEE International NEWCAS Conference.
My project goals are to propose novel low-power schemes and to modify traditional low-power techniques to reduce the power consumption of the clock distribution network with emphasis on the clock sink, i.e., the flip-flops operating under resonant (sinusoidal) clocking.
A new type of slack in the skew has been proposed [1], [2]. This new slack can be compensated for to reduce routing complexity in the clock network and as a byproduct achieve reduction in wire elongation, total wire length, and power. Simulation results illustrate that the proposed approach is feasible and effective where a reduction of 53% in the number of wire elongations has been achieved. In addition, a dual-edge clocking scheme introduced in the literature to enable the operation of the flip-flop at the rising- and falling edges of the clock has been modified. The interval by which the charging elements in the flip-flop are being switched-on was reduced causing a reduction in power consumption [3], [4]. Simulating the flip-flop in STMicroelectronics 90nm technology show correct functionality of the flip-flop with a resonant clock signal of 500MHz and a throughput of 1GHz under process, voltage, and temperature (PVT) variation. Modeling the resonant system with the proposed flip-flop illustrates that dual-edge triggering can achieve up to 58% reduction in power consumption. Furthermore, the application of low-swing clocking to resonant clock distribution network is being investigated. The proposed low-swing resonant clocking scheme operates with one voltage supply and does not require an additional supply voltage. The Differential Conditional Capturing Energy Recovery flip-flop introduced in the literature was modified to operate with a low-swing sinusoidal clock. The layout of a multiply and accumulate unit using the proposed flip-flop with the low-swing clock has been submitted for fabrication using TSMC 90nm technology. The power advantages of low-swing clocking will be investigated on-chip.
Though the project concentration is aimed at the flip-flop side, estimating the power savings achievable through dual-edge and low-swing clocking required estimating the power of the clock driver. In doing so, an analytical approach was introduced to estimate the required driver strength in the clock generator. Using the proposed approach early at the design stage eliminates the need for programmable switches in the driving circuit, thus reduces area and power overhead.
References
1- S. E. Esmaeili, A. M. Farhangi, A. J. Al-Khalili, G. E. R. Cowan, (January 2010) ‘Skew compensation in energy recovery clock distribution networks’, IET Computers and Digital Techniques, vol. 4, issue 1: 56 – 72
2- S. E. Esmaeili, A. J. Al-Khalili, G. E. R. Cowan, (December 2008) ‘A novel Approach for skew compensation in energy recovery clock distribution networks’, IEEE 20th International Conference on Microelectronics, IEEE-ICM: 365 – 368
3- S. E. Esmaeili, A. J. Al-Khalili, G. E. R. Cowan, (Accepted – May 2010) ‘Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks’, IET Computers and Digital Techniques, 16 pages
4- S. E. Esmaeili, A. J. Al-Khalili, G. E. R. Cowan, (June 2010) ‘Dual-edge triggered pulsed energy recovery flip-flops’, 8th IEEE International NEWCAS Conference.