Comparators are the key building blocks of a flash analog to digital converter (ADC).  An N-bit flash ADC requires 2^{(N -1)} comparators, 2^N resistors for a reference ladder, a sample-hold circuit and an encoder. Accurate comparators can be designed with a total area being very large. Another approach is to design the comparators with small sized transistors. This has the advantage of using less chip area. The device would also be faster and use less power.  However, minimum sized comparators have larger input referred offsets.

Comparator redundancy or reassignment can be used to combat comparator offset. Alternatively, calibration schemes can compensate for the offset, improving ADC performance and yield without additional comparators or the need for adders to combine comparator outputs. In this project, efficient schemes to directly calibrate out the effect of comparator offset are being investigated. The goal of this project is to implement a medium resolution flash ADC having a low energy per conversion step complete with on-chip calibration