
The list
below is not being updated. Please see my profile on google scholar instead:
Patent:
[P1] G. Cowan,
D. Friedman, M. Meghelli, “Architecture for maintaining constant
voltage
controlled oscillator gain,” 7741919. Issued June 22nd, 2010.
Journal
Papers:
[J7] S. Moazzeni, M. Sawan, and G. Cowan,
“Optimizing the PowerSensitivity Tradeoff in TRF
Receivers,” Analog Integrated
Circuits and Signal Processing (Springer) special issue from 2012 NEWCAS
(Solicited following the conference. Accepted)
[J6] S. Esmaeili, A. AlKhalili, and G. Cowan,
“LowSwing Differential Conditional Capturing FlipFlop for LC
Resonant Clock Distribution Networks,” IEEE Trans. on VLSI Systems, vol.
20, no. 8, Aug. 2012, pp. 15471551.
[J5] Y. Shen, B. Hraimel, X. Zhang, G. Cowan, K. Wu, and
T. Liu, “A Novel Analog Broadband RF Predistortion Circuit to
Linearize Electroabsorption Modulator in Multiband OFDM UltraWideband
Radio over Fiber System,” IEEE
Trans. on Microwave Theory and Techniques, vol. 58, no. 11, part
2, Nov. 2010, pp. 33273335.
[J4] S. Esmaeili, G. Cowan, and A. AlKhalili,
“DualEdge Triggered Sense Amplifier FlipFlop for Resonant Clock
Distribution Networks” IET
Computers and Digital Techniques, vol. 4, no. 6, Nov. 2010, pp.
499514.
[J3] S. Esmaeili*,
A. Farhangi^, A. AlKhalili, and G. Cowan, “Skew compensation in
energy
recovery clock distribution networks,” IET
Computers and Digital Techniques, vol. 4, no. 1, pp. 5672, Jan
2010.
[J2] A. Moradi*,
R. Raut, and G. Cowan, “Temperature compensation in gmC filters
using
resistive bridge,” IET Electronics
Letters, vol. 45, no. 18, pp. 921923, Aug 27^{th},
2009.
[J1] G. Cowan,
R. Melville, and Y. Tsividis, “A VLSI analog computer / digital
computer
accelerator,” Journal of SolidState
Circuits, vol. 41, no. 1, pp 4253, Jan. 2006.
Conference
Presentations:
[C27] A. Rabbani Abolfazli, Y. R. Shayan, G. E. R. Cowan,
“750Mb/s 17pJ/b 90nm CMOS (120, 75) TSLDPC MinSum based analog
decoder,” IEEE Asian SolidState Circuits Conference (Accepted).
[C26] M. Behbahani and G. Cowan, “PhaseNoise Tuneable Ring
VoltageControlled Oscillator in 90 nm CMOS,” IEEE MidWest
Symposium on Circuits and Systems, Columbus, OH, Aug. 2013.
[C25] C. Williams, O. LiboironLadouceur, and G. Cowan, “Power
and Noise Configurable PhaseLocked Loop Using MultiOscillator
Feedback Alignment,” IEEE MidWest Symposium on Circuits and
Systems, Columbus, OH, Aug. 2013.
[C24] P. Dash, O. LiboironLadouceur, and G. Cowan, “A Variable
Bandwidth, Power Scalable Optical Receiver FrontEnd in 65nm,”
IEEE MidWest Symposium on Circuits and Systems, Columbus, OH, Aug.
2013.
[C23] P. Dash, O. LiboironLadouceur, and G. Cowan,
“Inductorless, PowerProportional, Optical Receiver FrontEnd in
TSMC 90 nm,” IEEE International Symposium on Circuits and
Systems, Beijing, China, May 2013, pp. 11271130.
[C22] G. Cowan, C. Williams, “PhaseLocked Loop Architecture for
Enhanced VoltageControlled Oscillator PhaseNoise Suppression,”
IEEE International Symposium on Circuits and Systems, Beijing, China,
May 2013, pp. 24762479.
[C21] S. Moazzeni, G. Cowan, and M. Sawan, “A MismatchRobust
PeriodBased VCO Frequency Comparison Technique for ULP
Receivers,” IEEE International Symposium on Circuits and Systems,
Beijing, China, May 2013, pp. 17651768.
[C20] G. Cowan, M. Meghelli, D. Friedman, “A Linearized
VoltageControlled Oscillator for DualPath PhaseLocked Loops,”
IEEE International Symposium on Circuits and Systems, Beijing, China,
May 2013, pp. 26782681.
[C19] S. Esmaeili, R. Islam, A. AlKhalili, and G. Cowan,
“Dualedge triggered sense amplifier flipflop utilizing an
improved scheme to reduce area, power, and complexity,” 19th IEEE
International Conference on Electronics, Circuits and Systems (ICECS),
Dec. 2012, pp. 292295.
[C18] S. Moazzeni, G. Cowan, M. Sawan, “A comprehensive study on
the powersensitivity tradeoff in TRF receivers,” IEEE NEWCAS,
Montreal, Canada, June 2012, pp. 401404.
[C17] A. Rabbani Abolfazli, Y. R. Shayan, G. E. R. Cowan,
“TSLDPC Analog Decoding Based on the MinSum Algorithm,”
26th Biennial Symposium on Communications (QBSC), Kingston, Canada, May
2012, pp. 162167.
[C16] S. Esmaeili, A. Farhangi, A. AlKhalili, and G. Cowan
“Clock Tree Structure With Reduced Wire Length Using the
MatchedDelay Skew Compensation Technique,” Canadian Conference
on Electrical and Computer Engineering, Montreal, Canada, May 2012.
[C15] S. Moazzeni, G. Cowan, M. Sawan, “A 28μW SubSampling
Based WakeUp Receiver with 70dBm Sensitivity for 915MHz ISM Band
Applications,” International Symposium on Circuits and Systems,
Soeul, Korea, May 2012, pp. 27972800.
[C14] M. Naik, S. Magierowski, G. Cowan, and T. Zourntos,
“MixedMode IC Design of a Cyberphysical PathPlanner for
Miniature Robots,” 3rd International Conference on Computational
Intelligence and Software Engineering (CiSE 2011), Wuhan, China, Dec.
2011.
[C13] O. Ghasemi, R. Raut, G. Cowan, “Complex Conjugate Pole
Analysis for Bandwidth Extension of Transimpedance Amplifiers,”
IEEE Midwest Symposium on Circuits and Systems, Seoul, Korea, Aug. 2011.
[C12] M. JavanmardiNasab and G. Cowan, “Oscillatorbased
calibration architecture to reduce the impact of process variation on
CML,” 2nd European Workshop on CMOS Variability, VARI 2011,
Grenoble, France, May 2011.
[C11] S. Esmaeili, A. AlKhalili, and G. Cowan, “Estimating the
Required Driver Strength in the Resonant Clock Generator,” IEEE
APCCAS, Malaysia, Dec. 2010, pp. 927930.
[C10] S.
Esmaeili*, A. AlKhalili, and G. Cowan, “DualEdged Triggered
Pulsed Energy
Recovery FlipFlops,” IEEE NEWCAS 2010,
Montreal, Canada, June 2010.
[C9] S.
Esmaeili*, A. AlKhalili, and G. Cowan, “DualEdge Triggered
Energy Recovery
DCCER FlipFlop for Low Energy Applications,” 19th
European Conference on Circuit Theory & Design, Turkey,
Aug. 2009, pp 5760.
[C8] A.
Aryanpour* and G. Cowan, “A Circuit Design and Fabrication
Approach to Address
Global Process Variation”, IEEE MidWest
Symposium on Circuits and Systems, Mexico, Aug. 2009, pp. 455458.
[C7] S. Moazzeni*
and G. Cowan, “Application of Active Current Mirrors to Improve
the Speed of
Analog Decoder Circuits,” IEEE MidWest
Symposium on Circuits and Systems, Mexico, Aug. 2009, pp. 9497.
[C6] O. Ghasemi*,
R. Raut, and G. Cowan, “A Low Power Transimpedance Amplifier
Using Inductive
Feedback approach in 90nm CMOS,” IEEE
International Symposium on Circuits and Systems, Taiwan, May 2009,
pp.
19371940. [Flagship conference of the
IEEE Circuits and Systems Society]
[C5] S. Esmaeili*, A.
AlKhalili, and G. Cowan, “A
Study on the Effects of Temperature and Loading on the Power
Consumption in Energy
Recovery Resonant Clocking”, Information
Science and Technology, Kuwait, Mar. 2009, pp. 365368.
[C4] S. Esmaeili*,
G. Cowan, and A. AlKhalili, “A Novel Approach for Skew
Compensation in Energy
Recovery Clock Distribution Networks,” The
20^{th} International Conference on Microelectronics,
Sharjah, UAE,
Dec. 2008, pp. 365368.
[C3] S. Esmaeili*,
G. Cowan, and A. AlKhalili, “Power Reduction in Energy Recovery
and
SquareWave Clock Distribution Networks Operating at Half Frequency
with
DualEdge Triggered FlipFlops,” IEEE NEWCASTAISA
2008, June 2008, pp. 125 – 128.
[C2] Y.
Tsividis, G. Cowan, Y. W. Li, and K. Shepard, “ContinuousTime
DSPs,
Analog/Digital Computers and Other MixedDomain Circuits,” Proceedings of the 31st European SolidState Circuits
Conference
(ESSCIRC), 2005, pp 113116.
[C1] G. Cowan, R. Melville,
and Y. Tsividis, “A
VLSI analog computer/coprocessor for a digital computer,” Proceedings of the International SolidState Circuits
Conference
(ISSCC), February 2005, pp 8283, 586.
Workshop
presentations:
[W3] M. Behbahani and G. Cowan, “Variability
Mitigation Strategies in CML circuits: Design of a NoiseConfigurable
Voltage Controlled Oscillator,” CMOS
Emerging Technologies Workshop, Whistler, Canada, May 2010.
[W2] G. Cowan, Y. Tsividis, “Analog and Digital
ContinuousTime Computation and Signal Processing,” CMOS Emerging Technologies Workshop,
Banff, Canada, Feb 18th20th, 2009.
[W1] G. Cowan and
Y. Tsividis, “Analog
and Digital ContinuousTime Computation and Signal Processing,” Analog Decoding Workshop, Montreal,
Canada, May 2007, pp. 12.
Doctoral dissertation:
G. Cowan, “A VLSI Analog Computer/Math
Coprocessor for a Digital Computer”, Columbia University,
New York,
NY, 2005. (Eliahu I. Jury Award)

