Capstone Project

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Group 2007-23 Status completed
Title FPGAs based design and Implementation of an Emulation Environment
Supervisor Dr. Otmane Ait Mohamed
Description Demonstrate high speed communication between two Virtex-II Pro FPGA boards using Rocket IO interface available inside FPGAs. The data information can be generated using a RNG (Random Number Generator) inside the FPGA. The high level block diagram of the forward communication path is shown in Figure 1 and the reverse path would be the same. Verifying the data information at the receiver side is required.
Student Requirement � HDL language (preferably VHDL) � Programming skills, Assembly and a high level programming language such as C. � Able to use common electronic lab equipments. � General trouble shooting skills.
Tools � ISE and ModelSim or any other HDL simulator � EDK (in case of using MicroBlaze or Power PC processor) � C complier for processors (if needed)
Number of Students 4
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