| Description |
Emerging video-enabled products, such as mobile phones, digital cameras, iPods, portable TV devices, and video surveillance systems, continually demand for high quality video signals. However, video signals normally are corrupted with undesirable, yet inevitable, noise due to video acquisition, processing, storage or transmission. Thus, enhancing video signals by means of noise reduction algorithms is a fundamental step in many real-time vision systems. PDE-based techniques for image noise reduction have been extensively studied, and theoretically well understood. These iterative and "tunable" algorithms achieve visually better results as well as similar denoising gain in the PSNR sense, when compared to the other algorithms for image noise reduction.
The objective of this project is to design and implement an efficient FPGA-based architecture for a noise reduction algorithm. Students will be given to study a state-of-the-art PDE-based noise-filtering algorithm, and explore it for the hardware parallelism. The students will be guided to understand fundamental video-processing concepts of the algorithm to implement in hardware. The algorithm will be then modeled in MATLAB before coding it in VHDL. The architecture will efficiently utilize FPGA's inherent resources in order to maximize speed and minimize the area and power. Individual modules (components) will be verified with test benches, and then the overall functionality of the algorithm will be demonstrated with a top-level test bench.
In this project, students will have access to some VHDL simulation models such as DDR memory controllers, video acquisition and storage modules, and register interfaces.
Student Requirements: Students should have good knowledge in digital circuit design in VHDL. Fundamentals of FPGAs and signal/ processing are an asset.
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