Capstone Project
| Group | 2024-08 | Status | inprogress |
| Title | Wireline Transmitter | ||
| Supervisor | G. Cowan and Michael Venditti (Cadence Design Systems) | ||
| Description | As AI takes centre stage in many fields today, we see the widespread deployment of GPUs in the training and inference phases of neural networks. Their high data throughput puts extremely high demands on the interconnection networks between them, which, over short distances rely on copper wires such as cables or PCB traces. While copper is great for carrying large dc currents, its high-frequency losses limit transmit distance at the data rates of modern links, now exceeding 100 Gb/s per lane.
The team will design and construct a complete transmit path subsystem for a high-speed electrical link. The subsystem should use non-return-to-zero and support FIR-based equalization and impedance control. It should include duty-cycle-correction (DCC), serializer, and output driver functions. The serializer should support programmable modes of operation. The rate of operation for the transmit path should be as high as possible as permitted by the technology available. At a minimum, a functioning schematic representation of the overall subsystem is required. Layout implementations and post-extract simulation for some or all of the subsystem components is desirable – particularly for those constructed from digital standard cells. The complete transmit path subsystem should be able to demonstrate DCC correction in simple behavioral closed loop simulation and show the impact on the output driver characteristics. Performance with a representative channel (moderate/significant loss characteristics) should be demonstrated, showing the impact of FIR EQ on the far-end eye diagram characteristics. |
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| Student Requirement | The group should have students who did well in ELEC 312 and who are taking COEN 451 and are enrolled to take ELEC 413 in the winter. Other relevant courses would be ELEC 351, 372; COEN 314. Students will make heavy use of the Cadence suite of computer-aided IC design tools. Any previous experience is an asset. | ||
| Tools | Cadence ICFB tools | ||
| Number of Students | 5-6 | ||
| Students | Z.Y. Cui, J. Frendo-Cumbo, L. Hotton, M. Natesh, N-T Pham-Bui, | ||
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